The present invention relates to a memory device, and more particularly to a MOS random access memory which is so small in power consumption that it is possible to use a battery back-up for the memory.
In a conventional static memory, as described on pages 216, 217, and 341 of the February 1984 issue of the ISSCC Digest of Technical Papers and in a Japanese patent application specification (Publication No. 53-148989), each static memory cell is made up of six elements which include two load resistors for retaining data stored in the memory cell, and data can be read out from or written in a memory cell only by supplying the memory with an external address signal for specifying the memory cell. In other words, the conventional static memory is an asynchronous memory, which does not require any external control clock signal and hence is easy to use. Accordingly, the asynchronous memory is suited for forming a smallsized memory system. Further, the load resistor of the memory cell has a resistance of the order of 10.sup.10 .OMEGA., and a stand-by current less than 10 .mu.A per chip (for example, a stand-by current of 2 .mu.A for a supply voltage of 5 V) can be realized for a memory including 64K bits per chip. Thus, the battery back-up can be made for the above memory. However, the conventional static memory has the following drawbacks, thereby making it impossible to fabricate a static memory which has a higher integration density than usual, and for which the battery back-up can be made. FIG. 9 shows a conventional static memory cell. In FIG. 9, reference numerals 1 and 2 designate transfer transistors each formed of an n-channel MOS transistor, 3 and 4 driver transistors each formed of an n-channel MOS transistor, 5 and 6 data lines, 7 a word line, 8 and 9 data storing nodes, 10 a ground line having a potential V.sub.ss, 111 a power source line having a potential V.sub.cc, and 112 and 113 load resistors. The data at the nodes 8 and 9 is maintained by supplying a current from the power source line 111 to each node. The same polysilicon layer as used for forming the gates of the MOS transistors 1 to 4 or a laminated polysilicon layer different from the polysilicon layer used for forming the above gates, is used for forming the load resistors 112 and 113, and part of the polysilicon layer or laminated polysilicon layer is left as an intrinsic or low-doped semiconductor region in order for the load resistors 112 and 113 to have a desired resistance value.
The memory cell of FIG. 9 has the following drawbacks. Firstly, the resistance value of each of the load resistors 112 and 113 varies greatly depending upon manufacturing conditions, and is difficult to control. Further, the above resistance value varies non-linearly with the voltage applied across the load resistor. In order to reduce the power consumption of a large static RAM (including 256k bits or 1M bits per chip) so that the battery back-up can be made for the RAM, that is, in order for the RAM to have a stand-by current of 2 .mu.A for a supply voltage of 5 V, it is necessary to make the resistance value of a load resistor four or sixteen times larger than the resistance value now used. In this case, however, there arises a problem mentioned below. A load resistor connected to a high-potential node which has to be supplied with a current, has a small terminal voltage. Owing to the above-mentioned non-linear variation of the resistance value of a load resistor with the voltage applied across the load resistor, the resistance value of the load resistor on the high-potential node side becomes larger than the resistance value thereof in a case where a supply voltage of 5 V is applied across the load resistor, by about one order of magnitude. In other words, a current supplied to the high-potential node is smaller, as compared with a case where a supply voltage of 5 V is applied across the load resistor on the low-potential node side, by about one order of magnitude, and in the above case becomes nearly equal to a leak current at a connecting point of the high-potential node. Thus, the memory cell cannot retain data statically.
Secondly, the resistance value of the load resistor is greatly dependent on the scaling principle of MOS device. The inventors' experiment on the load resistor formed of an intrinsic polysilicon layer, showed that when the length of the load resistor was made less than 4 .mu.m, a punch-through current flowed through the load resistor, and thus it was impossible to keep the low current characteristics. That is, even when the MOS transistors included in a memory cell are made small in size to make small the area occupied by the memory cell, it is impossible to make small the size of the load resistor which is indispensable for the memory cell. As mentioned above, it is impossible to realize a static RAM which is large in the number of bits per chip, and for which the battery back-up can be made.
Thirdly, the memory cell is made up of six elements, and hence is large in size. This also makes it difficult to fabricate a static RAM which is large in the number of bits per chip.
A conventional dynamic memory is made up of memory cells each of which does not include a load resistor for retaining data, and hence is small in size. Accordingly, the dynamic memory can be made large in the number of bits per chip. However, each memory cell of the dynamic memory is a volatile cell, and hence a refresh operation has to be made for the memory cell. Accordingly, an external control signal for the refresh operation is indispensable for the dynamic memory, and thus the dynamic memory is obliged to be a synchronous memory, which is hard to use.